ASIC Front End Designer Intern

Responsibilities ? RTL design for the following types of SOC building blocks: o Embedded CPU clusters o Video processing pipe o Media interfacing block o I/O blocks (DDR, USB, Ethernet, I2C, I2S, SPI, etc.) ? Study relevant IP architecture, configuration, and programming model, integrate IP into the block. ? Verify functionality of the block using UVM/VIP based verification environment provided by the verification team. ? Design and maintain block level test cases. Debug test failure. ? Work with FPGA emulation team to bring the design to the FPGA emulation platform, port and extend simulation testcases to the FPGA environment. ? Support silicon bring up and debug. ? Support software team for hardware related issues. Qualifications Qualification ? Experience of RTL/Verilog coding ? Have strong logical reasoning skills ? Knowledge of UVM is a plus ? Knowledge of FPGA is a plus ? Willing to learn


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