Junior-Intermediate ASIC Design Engineer - Video-Image Processing

Current market has been asking for better solutions for capturing, analyzing, compressing, and transporting video streams at higher resolution and better quality. Lions project addresses these requirements with an SoC platform based solution that will integrate leading technologies of video processing, video analytics, video compression and networking. As a member of the SoC design team, you will work with the SoC design verification team, FPGA emulation team, and software team, to implement building blocks of the SoC, bring it from concept to the final silicon.


  • RTL design for the following types of SOC building blocks:
    • Embedded CPU clusters
    • Video processing pipe
    • Media interfacing block
    • I/O blocks (DDR, USB, Ethernet, I2C, I2S, SPI, etc.)
  • Study relevant IP architecture, configuration, and programming model, integrate IP into the block.
  • Verify functionality of the block using UVM/VIP based verification environment provided by the verification team.
  • Design and maintain block level testcases. Debug test failure.
  • Work with FPGA emulation team to bring the design to the FPGA emulation platform, port and extend simulation testcases to the FPGA environment.
  • Support silicon bring up and debug. ? Support software team for hardware related issues.


  • BS or M.S. EE/CS/CE, with interest and experience in VLSI. New graduates are welcome.
  • Knowledge and experience of RTL coding and simulation using Verilog.
  • Knowledge of digital logic design, solid understanding of synchronous design, basic building structure such as FSM, FIFO, arbiter, etc.

Experience of any of the following technology is highly desirable:

  • Video codec
    • Camera interfacing and ISP
    • Computer architecture
    • High speed I/O (DDR, USB, Ethernet, etc.)
    • Knowledge and experience of UVM is a plus.
    • Self-starter with the mindset to handle complicated technology challenges under pressure.

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